The invention relates to a method for designing a synchronous digital electronic circuit that comprises cells and clocked flipflops interconnected by nets and running at a predetermined clock period, through selective positioning of said flipflops, wherein any cell of the circuit imparts to a path between an input/output pair of the cell a respective signal delay, and wherein in-circuit paths imparting a total delay above said clock period are being provided with at least one flipflop. If the granularity considered in the design of the circuit is fine, a cell or node may be an essentially unclocked combinatorial element. In case of coarser granularity a node may comprise one or more clocked elements, or broader, sequentially operating elements. Moreover, the relevance of the clocked element may depend on the actual signal path through the node considered, as will be explained hereinafter. A method according to the preamble has been described in the paper `Retiming Synchronous Circuitry` by Ch. E. Leiserson and J. B. Saxe, published in Algorithmica '91 pp. 5-35. Especially the introduction of Digital Signal Processing (DSP) for video signals has increased the requirements for signal throughput, which would in fact necessitate putting flipflops closer to each other, in terms of the number of interposed cells. A particular technique in the reference is repositioning of the flipflops or "retiming" to enhance the performance, and in particular, allowing for higher clock frequencies. A subset or special case of retiming is pipelining. These two techniques will be discussed hereinafter. According to the reference, circuit latency is not increased. The reference operates by setting up matrices of inter-cell signal delays and providing flipflops to all inter-cell paths that show a delay time that is larger than one clock period. Subsequently, the flipflops are subjected to retiming or shifting. However, the solving of the many conditions is not efficient for large circuits, inter alia, because of the lengthy path that may interconnect an arbitrary pair of cells, and the great number of such conditions in view of the great number of cells.